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a
50 mA Switched Capacitor Voltage Boost with Regulated Output ADP3607
FUNCTIONAL BLOCK DIAGRAM
CP+ CP-
FEATURES Fully Regulated Output Voltage (5 V and Adjustable) Input Voltage Range From 3 V to 5 V 50 mA Output Current Output Accuracy: 5% High Switching Frequency: 250 kHz SO-8 and TSSOP-8 Packages -40 C to +85 C Ambient Temperature Range APPLICATIONS Computer Peripherals and Add-On Cards Portable Instruments Battery Powered Devices Pagers and Radio Control Receivers Disk Drives Mobile Phones
V
S1 IN S4
S3
S2
V
OUT
SD
OSC CLOCK GEN FB 1.5 V VREF V
SENSE
GENERAL DESCRIPTION
GND
The ADP3607 is a 50 mA regulated output switched capacitor voltage doubler. It provides a regulated output voltage with minimum voltage loss and requires a minimum number of external components. In addition, the ADP3607 does not require the use of an inductor. The internal oscillator of the ADP3607 runs at 500 kHz nominal frequency, which produces an output switching frequency of 250 kHz. This allows for the use of smaller charge pump and filter capacitors. The ADP3607 provides an accuracy of 5% with a typical shutdown current of 150 A. It can also operate from a single positive input voltage as low as 3 V. The ADP3607 is offered with the regulation fixed at 5 V, or adjustable via external resistors over a 3 V to 9 V range.
VIN 3.3V *CIN+ 4.7 F *CP 4.7 F +
SD103 D1 VIN CP+ VOUT
+
*CO 4.7 F
VOUT 5.0V
ADP3607-5
CP -
SD OFF ON 0
GND
VSENSE
*FOR BEST PERFORMANCE, 10 F IS RECOMMENDED CP : SPRAGUE, 293D475X0010B2W CIN, CO: TOKIN, 1E475ZY5UC205F
Figure 1. Typical Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3607-SPECIFICATIONS1, 2, 3(V
Parameter OPERATING SUPPLY RANGE SUPPLY CURRENT Shutdown Mode OUTPUT VOLTAGE4 VO VO Symbol VS IS
IN
= 3.3 V @ TA = +25 C, CP = CO = 4.7 F unless otherwise noted.)
Min 3.0 Typ 3.3 3.5 150 4.85 4.75 5 5 Max 5 6 200 5.15 5.25 Units V mA A V V
Condition
-40C < TA < +85C VSD = VIN, -40C < TA < +85C IO = 25 mA IO = 10 mA to 50 mA -40C TA +85C 3.0 V VS 3.6 V IO = 10 mA-25 mA IO = 10 mA-50 mA CIN = CO = 4.7 F ILOAD = 25 mA ILOAD = 50 mA VIN = 3.3 V -40C < TA < +85C 212 2.4
LOAD REGULATION OUTPUT RESISTANCE (Open Loop) OUTPUT RIPPLE VOLTAGE
VO/IO RO VRIPPLE
0.3 0.25 11 16 31 250 288
mV/mA mV/mA mV mV kHz V A V A
SWITCHING FREQUENCY SHUTDOWN Logic Input High Input Current Logic Input Low Input Current
fS
VIH IIH VIL IIL
1 0.4 1
NOTES 1 Capacitors CIN, CO and CP in the test circuit are 4.7 F with 0.1 ESR. Capacitors with higher ESR may reduce output voltage and efficiency. 2 See Figure 1 conditions. 3 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 4 For the adjustable version, a 1% resistor should be used to maintain output voltage tolerance. For both device types, tolerances can be improved by >1% using larger value and lower ESR capacitors for C O and C P. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
ORDERING GUIDE
Input Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . +7.5 V Output Voltage (VOUT to GND) . . . . . . . . . . . . . . . . . . +12 V Output Short Circuit Protection . . . . . . . . . . . . . . . . . . . 1 sec JA, SO-8 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W JA, TSSOP-8 Package2 . . . . . . . . . . . . . . . . . . . . . . 208C/W Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 This is a stress rating only, operation beyond these limits can cause the device to be permanently damaged. 2 JA is specified for worst case conditions with device soldered on a circuit board.
Model ADP3607AR-5 ADP3607AR ADP3607ARU-5 ADP3607ARU
Output Voltage 5 V, 50 mA Adjustable, 50 mA 5 V, 50 mA Adjustable, 50 mA
Package Option* SO-8 SO-8 RU-8 RU-8
*SO = Small Outline Package; RU = Thin Small Outline Package. Contact the factory for the availability of other output voltage options.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3607 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-2-
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ADP3607
Table I. Other Members of ADP360x Family 1 Output Current 50 mA 120 mA 120 mA 120 mA Package Option2 SO-8 SO-8 SO-8 SO-8 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic
Comments Nom. -3 V 3% Inverter Nom. -3 V 3% Inverter Nom. -3 V 5% Inverter Adj. Output Inverter
Function Positive Terminal for the Pump Capacitor. Input Voltage. Connect a low ESR bypass capacitor between this pin and device ground to minimize supply transients. Negative Terminal for the Pump Capacitor. Logic Level Shutdown. Apply a logic Hi or connect to VIN to shut down the device. In Shutdown mode, the charge pump is turned off and quiescent current is reduced. Apply a logic low or connect to ground for normal operation. Output Voltage Sense Line. This is used to improve load regulation by eliminating IR drops on the high current carrying output traces. For normal operation, connect VSENSE to VOUT. See Application Information section for more detail. No Connection. Ground. Regulated Output Voltage. Connect a low ESR, 4.7 F or larger capacitor between this pin and device GND.
PIN CONFIGURATION
Model ADP3603AR ADP3604AR ADP3605AR-3 ADP3605AR
1 2
CP+ VIN
NOTES 1 See individual data sheets for detailed ordering information. 2 SO = Small Outline package.
3 4
CP - SD
Table II. Alternative Capacitor Technologies
Type
Aluminum Electrolytic Capacitor Multilayer Ceramic Capacitor Solid Tantalum Capacitor OS-CON Capacitor
Life
High Freq
Temp
Size
Cost
5
VSENSE
Fair
Fair
Fair
Small
Low
Long
Good
Poor
Fair
High
6 7 8
NC GND VOUT
Above Avg Above Avg
Avg Good
Avg Good
Avg Good
Avg Avg
Table III. Recommended Capacitor Manufacturers
CP+ 1
8 VOUT
Manufacturer Sprague Sprague Nichicon Mallory TOKIN MuRata
Capacitor 672D, 673D, 674D, 678D 675D, 173D, 199D PF and PL TDC and TDL MLCC GRM
Capacitor Type Aluminum Electrolytic Tantalum Aluminum Electrolytic Tantalum Multilayer Ceramic Multilayer Ceramic
7 GND TOP VIEW CP- 3 (Not to Scale) 6 NC
VIN 2
ADP3607
SD 4
5 VSENSE
NC = NO CONNECT
REV. 0
-3-
ADP3607 -Typical Performance Characteristics
270
4.00
OSCILLATOR FREQUENCY - kHz
SUPPLY CURRENT - mA
265
3.75 VIN = +5.0V 3.50
VIN = +4.0V
260
255
3.25 VIN = +3.0V
VIN = +3.3V
250 3.0
3.5
4.0 4.5 SUPPLY VOLTAGE - Volts
5.0
3.00 -40
-15
10 35 TEMPERATURE - C
60
85
Figure 2. Oscillator Frequency vs. Supply Voltage
Figure 5. Supply Current vs. Temperature in Normal Mode
5.05
300
OSCILLATOR FREQUENCY - kHz
5.03
280
OUTPUT VOLTAGE - Volts
IL = 10mA 5.01 IL = 25mA
260
4.99 IL = 50mA 4.97
240
220
4.95 -40
-15
10 35 TEMPERATURE - C
60
85
200 -40
-15
10 35 TEMPERATURE - C
60
85
Figure 3. Output Voltage vs. Temperature
Figure 6. Oscillator Frequency vs. Temperature
125
5.05 5.00
AVERAGE INPUT CURRENT - mA
100
OUTPUT VOLTAGE - Volts
4.95 4.90 4.85 VIN = +3.3V 4.80 VIN = +3.0V 4.75 VIN = +5.0V VIN = +4.0V
75
50
25
0
4.70 10 15 20 25 30 35 40 OUTPUT CURRENT - mA 45 50 0 25 50 75 125 100 LOAD CURRENT - mA 150 175 200
Figure 4. Average Input Current vs. Output Current
Figure 7. Output Voltage vs. Load Current
-4-
REV. 0
ADP3607
3.7 300 250
SUPPLY CURRENT - mA
FIXED VERSION
SUPPLY CURRENT -
A
3.6
200 FIXED VERSION 150
3.5 ADJUSTABLE VERSION R = 38k 3.4
100
ADJUSTABLE VERSION R = 38k
50
3.3 3.0
3.5
4.0 4.5 SUPPLY VOLTAGE - Volts
5.0
0 3.0
3.5
4.0 4.5 SUPPLY VOLTAGE - Volts
5.0
Figure 8. Supply Current vs. Supply Voltage in Normal Mode
Figure 11. Supply Current vs. Supply Voltage in Shutdown Mode
240 VIN = +5.0V 220 A
80 70 60
SUPPLY CURRENT -
EFFICIENCY - % 60 85
200 VIN = +4.0V 180
50 40 30 20
160
VIN = +3.3V
140 VIN = +3.0V 120 -40 -15 10 35 TEMPERATURE - C
10 0 0
10
20 30 LOAD CURRENT - mA
40
50
Figure 9. Supply Current vs. Temperature in Shutdown Mode
Figure 12. Efficiency vs. Load Current Based on Circuit of Figure 1
VO = +5.0V VOUT VO = 0V VIN = +3.3V T CH1 2.00V CH2 2.00V M2.00ms CH2 VIN = 0V 1.12V
VO = +5.0V VOUT VO = +4.96V IO = 50mA IL IO = 1mA CH2 20.0mV CH4 10.0mV BW M4.00 s CH4 BW 9.0mV
VIN
Figure 10. Start-up Under Full Load Based on Circuit of Figure 1
Figure 13. Load Transient Response Based on Circuit of Figure 1
REV. 0
-5-
ADP3607
THEORY OF OPERATION
The ADP3607 uses a switched capacitor principle to generate a regulated boost voltage from a positive input voltage. An on-board oscillator generates a two-phase clock to control a switching network that transfers charge between the storage capacitors. The switches turn on and off at a 250 kHz rate that is generated from an internal 500 kHz oscillator. The basic principle behind the voltage conversion scheme is illustrated in Figures 14 and 15.
VIN S1 CP S4 + - S3 S2 VOUT
When selecting the capacitors, keep in mind that not all manufacturers guarantee capacitor ESR in the range required by the circuit. In general, the capacitor's ESR is inversely proportional to its physical size, so larger capacitance values and higher voltage ratings tend to reduce ESR. Since the ESR is also a function of the operating frequency, when selecting a capacitor make sure its value is rated at the circuit's operating frequency. Another factor affecting capacitor performance is temperature. Figure 16 illustrates the temperature effect on various capacitors. If the circuit has to operate at temperatures significantly different from +25C, the capacitance and ESR values must be carefully selected to adequately compensate for the change. Various capacitor technologies offer improved performance over temperature; for example, certain tantalum capacitors provide good low temperature ESR but at a higher cost. Table II provides the ratings for different types of capacitor technologies to help the designer select the right capacitors for the application. The exact values of CIN and CO are not critical. However, low ESR capacitors such as solid tantalum and multilayer ceramic capacitors are recommended to minimize voltage loss at high currents. Table III shows a partial list of the recommended low ESR capacitor manufacturers.
40
Figure 14. ADP3607 Switch Configuration Charging the Pump Capacitor
During phase one, S1 and S3 are ON, charging the pump capacitor to the input voltage. Before the next phase begins, S1 and S3 are turned OFF, as are S2 and S4 to prevent any overlap. S2 and S4 are turned ON during the second phase (see Figure 15) and charge stored in the pump capacitor is transferred to the output capacitor.
VIN S1 CP S4 + - S3 S2 VOUT
ADP3607-5 35
OUTPUT RIPPLE - mV
30 ILOAD = 50mA 25 20 150m 15 100m 10 50m 5 0 20 40 60 80 CAPACITANCE - 100 F 120 140
Figure 15. ADP3607 Switch Configuration Charging the Output Capacitor
During the second phase, the negative terminal of the pump capacitor is connected to VIN through variable resistance switch S4, and the positive terminal is connected to the output, resulting in a voltage shift at the output terminal. The ADP3607 block diagram is shown on the front page.
10 ALUMINUM
Figure 17. Output Ripple Voltage (mV) vs. Capacitance and ESR
1.0 CERAMIC
Input Capacitor
TANTALUM 0.1 ORGANIC SEMIC
A small 1 F input bypass capacitor (preferably with low ESR) such as tantalum or multilayer ceramic, is recommended to reduce noise and supply transients, and supply part of the peak input current drawn by the ADP3607. A large capacitor is recommended if the input supply is connected to the ADP3607 through long leads, or if the pulse current drawn by the device might affect other circuitry through supply coupling.
0 50 TEMPERATURE - C 100
ESR -
0.01 -50
Output Capacitor
Figure 16. ESR vs. Temperature
APPLICATION INFORMATION Capacitor Selection
The ADP3607's high internal oscillator frequency permits the use of small capacitors for both the pump and the output capacitors. For a given load current, factors affecting the output voltage performance are: * Pump (CP) and output (CO) capacitance. * ESR of the CP and CO. -6-
The output capacitor (CO) is alternately charged to the CP voltage when CP is switched in parallel with CO. The ESR of CO introduces steps in the VOUT waveform whenever the charge pump charges CO, which contributes to VOUT ripple. Thus, ceramic or tantalum capacitors are recommended for CO to minimize ripple on the output. Figure 17 illustrates the output ripple voltage effect for various capacitance and ESR values. Note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the ESR, no significant reduction in VOUT ripple is achieved by added capacitance. Since output current is supplied solely by REV. 0
ADP3607
the output capacitor, CO, during one-half of the charge-pump cycle, peak-to-peak output ripple voltage is calculated by using the following formula. Because of the external Schottky diode between VIN and VOUT, the output voltage will be held to a diode drop below VIN when the ADP3607 is in shutdown mode.
Power Dissipation
VRIPPLE =
where IL = Load Current
IL 2 x FPUMP x CO
+ 2 x I L x ESRCO
The power dissipation of the ADP3607 circuit must be limited such that the junction temperature of the device does not exceed the maximum junction temperature rating. Total power dissipation is calculated as follows:
P = (2 VIN - VOUT) IOUT + (VIN) IS
FPUMP = 250 kHz nominal switching frequency CO = 10 F with an ESR of 0.15 VRIPPLE = 50 mA + 2 x 50 mA x 0.15 = 25 mV 2 x 250 kHz x 10 F
Where IOUT and IS are output current and supply current, VIN and VOUT are input and output voltages respectively. For example: assuming worst case conditions, VIN = 5 V, VOUT = 5 V, IOUT = 50 mA and IS = 6 mA. Calculated device power dissipation is:
P (2 x 5 V - 5 V)(0.05 A) + (5 V)(0.006 A) = 280 mW
Multiple smaller capacitors can be connected in parallel to yield lower ESR and potential cost savings. For lighter loads, proportionally smaller capacitors are required. To reduce high frequency noise, bypass the output with a 0.1 F ceramic capacitor in parallel with the output capacitor.
Pump Capacitor
This is far below the 660 mW power dissipation capability of the ADP3607.
General Board Layout Guidelines
The ADP3607 alternately charges CP to the input voltage when CP is switched in parallel with the input supply, and then transfers charge to CO when CP is switched in parallel with CO. During the time CP is charging, the peak current is approximately two times the output current. During the time CP is delivering charge to CO, the supply current drops down to about 3 mA. A low ESR capacitor has much greater impact on performance for CP than CO since current through CP is twice the CO current. Therefore, the voltage drop due to CP is about four times the ESR of CP times the load current. While the ESR of CO affects the output ripple voltage, the voltage drop generated by the ESR of CP, combined with the voltage drop due to the output source resistance, determines the maximum available VOUT.
Improved Load Regulation
Since the ADP3607's internal switches turn on and off very quickly, good PC board layout practices are critical to ensure optimal operation of the device. Improper layouts will result in poor load regulation, especially with heavy loads. Following these simple layout guidelines will improve output performance. 1. Use adequate ground and power traces or planes. 2. Use single point ground for device ground and input and output capacitor grounds. 3. Keep external components as close to the device as possible. 4. Use short traces from the input and output capacitors to the input and output pins respectively.
Maximum Output Voltage
In most applications, IR drops due to printed circuit board traces are not critical. VSENSE should be connected to the output at a convenient pcb location close to the load. However, if a reduction in IR drops, or improvement in load regulation is desired, the sense line can be used to monitor the output voltage at the load. To avoid excessive noise pickup, keep the VSENSE line as short as possible and away from any noisy line.
Shutdown Mode
Maximum unregulated output voltage can be obtained by connecting the VSENSE pin to ground instead of to the VOUT pin (see Figure 18). Under this condition, the magnitude of the unregulated output voltage depends on the load current. VOUT is inversely proportional to the load current.
7.3 7.1 VIN = 3.6V
The ADP3607's output can be disabled by pulling the SD Pin to a TTL /CMOS logic high level which will stop the internal oscillator. Applying a logic low will turn ON the oscillator. If the shutdown feature is not used, the SD pin should be tied to ground. The shutdown mode current is dominated by the resistor divider connected to the VSENSE pin. This current can be calculated using one of the following formulas. 5 V fixed output version:
OUTPUT VOLTAGE - Volts
6.9 6.7 VIN = 3.3V 6.5 6.3 6.1 5.9 5.7
VIN CIN 4.7 F
IN5819 D1 +
CP + 4.7 F VIN VOUT CP+ VSENSE CP- SD GND
VO +
CO 4.7 F
I SENSE(SD ) =
Adjustable output version:
(VIN - 0.3V ) 23.75 k
5.5 0 5 10 15 20 25 30 35 OUTPUT CURRENT - mA 40 45 50
Figure 18. Maximum Unregulated Output Voltage
I SENSE(SD )
where REXT is in k. REV. 0
(VIN - 0.3 V ) = (9.5 k + REXT )
-7-
ADP3607
Regulated Adjustable Output Voltage
For the adjustable version of the ADP3607, the regulated output voltage is programmed by a resistor that is inserted between the VSENSE and VOUT pins, as illustrated in Figure 19. The inherent limit of the output voltage of a single doubling charge pump stage is two times the input voltage. The scaling factor of 2.00 is reduced somewhat due to losses that increase with output current. To increase the scaling factor to attain a more positive output voltage, an external pump stage can be added with just passive components as shown in Figure 20. That single stage increases the scaling factor to a limit of 3, although the diode drops will limit the ability to noticeably attain that exact 3.00 scaling factor. Even further increases can be achieved with more external pump stages. High accuracy on the adjustable output is achieved through the use of precision trimmed internal resistors, which eliminates the need to trim the external resistor or add a second resistor to form a divider. The adjustable output voltage is set using the following formula:
VOUT = R +1 9.5
D3 IN5819 C1 4.7 F + D2 SD103 +C 12V D1 1N5819 +C
O2
4.7 F
ADP3607
CP + 4.7 F CP+ CP- VSENSE VIN CIN 4.7 F + VIN SD GND VOUT
O
4.7 F
Figure 20. Regulated 12 V from a 5 V Input
Regulated Dual Supply System
The circuit in Figure 21 provides regulated positive and negative voltages for systems that require dual supplies from a single battery or power supply.
where VOUT is in volts and R is in ks.
6.5
VIN = +3.3V
SD103
ADP3607-5
R = 47.5k
10 F + CP1 10 F + VIN CP+ CP- SD
IN5819 D1 VIN = 3.3V CIN + CP 4.7 F + VIN VOUT CP+ VSENSE CP- SD GND VO
VOUT
+C
+5V
O1
6.0
10 F VSENSE GND
OUTPUT VOLTAGE - Volts
5.5
5.0
R
+
CO 4.7 F
ADP3605
VIN CP2 10 F CP+ CP- SD GND VOUT -2.6V R1 16.5k 1% CO2 +10 F
4.5
4.7 F
4.0 R = 24.9k 3.5 0 5 10 15 20 25 30 35 OUTPUT CURRENT - mA 40 45 50
+
VSENSE
Figure 19. Regulated Adjustable Output Voltage
Figure 21. Regulated Dual Supply System
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.122 (3.10) 0.114 (2.90)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
8
5
0.177 (4.50) 0.169 (4.30)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
PIN 1
0.256 (6.50) 0.246 (6.25)
1 4
0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8 0 0.0500 (1.27) 0.0160 (0.41)
0.0256 (0.65) BSC 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0118 (0.30) 0.0075 (0.19)
0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-8-
REV. 0
PRINTED IN U.S.A.
8-Lead SOIC (SO-8)
8-Lead TSSOP (RU-8)
C3500-8-8/99
R1 104.5k

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